Network synchronization technique

ABSTRACT

A network synchronization method allows reduced frequency fluctuations due to synchronization control in a network. Each node connected to the network has time information individually varying in a period of T. A time master node periodically notifies its own time information to time slave devices. Each time slave node prepares update-possible time points having a period of T/N (N&gt;1). When receiving master time information, each time slave node updates its own time information using the master time information at an update-possible time point just after the master time information has been received.

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

This application is a division of application Ser. No. 10/170,540, filedJun. 14, 2002, now pending, and based on Japanese Patent Application No.2001-181220 filed Jun. 15, 2001, by Wataru Domon. This applicationclaims only subject matter disclosed in the parent application andtherefore presents no new matter.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a communication network allowingtransport of real-time information such as motion picture in conformitywith standard specification of a high-speed serial bus such as IEEE 1394Serial Bus Standard and, in particular, to network synchronizationtechniques allowing data communication among nodes connected thereto.

2. Description of the Related Art

The IEEE 1394 standard is an international standard for implementing acost-effective and high-speed digital interface. An IEEE1394 interfaceprovides high-speed data transport of several hundreds of megabits persecond, a high affinity for real-time transport required for digitalvideo data transmission, and usability features. Accordingly, the IEEE1394 digital interface is caused to provoke widespread attention as anetwork interface for both computer peripherals and consumer electronicsincluding digital video cameras and digital television sets.

FIG. 1, as a typical example, shows a network for data transport inconformity with the IEEE 1394 standard. In general, the IEEE 1394defines physical layer, link layer, transaction layer, and serial busmanagement. On these layers an application layer is usually implementedas an upper layer. In FIG. 1, those layers that do not directly relateto the present invention are omitted for the sake of simplicity.

As shown in FIG. 1, an IEEE1394 network is composed of a plurality ofnodes each having physical layer (PHY) device, which are connected incascade through predetermined cables. Here, the port of PHY device 10 isconnected to a port of PHY device 11 by a cable 60 and the other port ofthe PHY device 11 is connected to a port of PHY device 12 by a cable 61.

An IEEE1394 PHY device has a repeater function of inputting data on oneport and outputting the data on all other ports thereof. Accordingly,the network of FIG. 1 is physically formed in tree topology butlogically in bus topology. Hereinafter, a PHY device is referred to as aPHY LSI (large scale integration) because a PHY device is usuallyavailable as an LSI.

A PHY LSI operates according to a clock signal generated by an externalcrystal oscillator. In FIG. 1, the respective PHY LSIs 10-12 havecrystal oscillators 30-32 attached thereto.

The resonance frequency f_(r) of a crystal oscillator is 24.576 MHz witha permissible deviation of ±100 ppm (parts per million). The IEEE1394standard defines transport rates: S100, S200, and S400, which correspondto 4×f_(r) (98.304 Mbits per second), 8×f_(r) (196.608 Mbits persecond), and 16×f_(r) (393.216 Mbits per second), respectively. Since aclock signal at each node is in free-running state without frequencysynchronization control, the PHY LSIs 10-12 may be operating inaccordance with different clock frequencies within the permissibledeviation of ∓100 ppm.

To achieve real-time data transport in such an IEEE1394 PHYcircumstance, an isochronous cycle mode has been introduced in theIEEE1394 standard. In the isochronous cycle mode, only a node that hasobtained a necessary bandwidth and gotten the right to transmit cantransmit an isochronous stream packet. Since the isochronous cycleoccurs in a period of 125 μsec, it ensures real-time transport of astream of data.

The isochronous cycle starts after transmission of a cycle start packet,which is transmitted by a node functioning as a cycle master. In FIG. 1,it is assumed that the node 50 is the cycle master. The cycle startpacket includes time information at which the packet itself wastransmitted. A cycle time register provides this time information. Inthis example, the cycle master 50 writes a value of its own cycle timeregister 40 on a cycle start packet when transmitting it to the IEEE1394bus.

As shown in FIG. 2, a cycle time register has a length of 32 bits, whichis divided into 7-bit second count field, 13-bit cycle count field, and12-bit cycle offset field.

The cycle offset field is a counter which counts according to a physicallayer clock of 24.576 MHz such that a counter value is incremented byone from 0 to 3071 before resetting to zero and starting again.Accordingly, the counter value is reset to zero at intervals of 125μsec.

The cycle count field is a counter which counts at intervals of 125μsec. Its counter value is incremented by one when the cycle offsetfield is reset to zero, from 0 to 7999 before resetting to zero andstarting again, and therefore it is reset to zero at intervals of 1second.

The second count field is a counter which counts at intervals of 1second. Its counter value is incremented by one when the cycle countfield is reset to zero, from 0 to 127 before resetting to zero andstarting again.

In general, a cycle time register (40, 41, 42) is implemented in a spaceof a control and status register (CSR) provided in the serial busmanagement (not shown). Accordingly, in FIG. 1, a link layer LSI (20,21, 22) is separated from a corresponding cycle time register (40, 41,42). However, the cycle time register is usually also implemented in thelink layer LSI. The link layer LSI (20, 21, 22) operates according to aclock frequency of 49.152 MHz, which is twice the physical layer clockfrequency of 24.576 MHz. In the link layer LSI, the clock frequency of49.152 MHz is divided by 2 to produce the physical layer clock frequencyof 24.576 MHz, which causes the cycle time register to operate.

Any node other than the cycle master receives the cycle start packetincluding the time information from the cycle master and overwrites aclock cycle offset value of its own cycle time register with thereceived time information to synchronize to the cycle master. In thismanner, the contents of the cycle time register of each node areadjusted ever time the cycle start packet is received at intervals of125 μsec so as to establish time information synchronization of allnodes.

For example, as shown in FIGS. 3A-3C, the time informationsynchronization is performed among the nodes 50-52. In this example, itis assumed that the PHY clock frequency of the crystal oscillator 31 inthe node 51 is higher than that of the crystal oscillator 30 in the node50 (cycle master) and the PHY clock frequency of the crystal oscillator32 in the node 52 is lower than that of the crystal oscillator 30.

For the sake of simplicity, it is further assumed that the cycle startpacket is transmitted when the cycle offset value of the cycle timeregister 40 is reset from 3071 to zero at the rising edge of the PHYclock and the time information written in the cycle start packet is acycle offset value of zero, that the other nodes 51 and 52 receive thecycle start packet from the cycle master 50 without delay, and that theoverwriting of the cycle offset at the nodes 51 and 52 is performed atthe rising edge of the PHY clock.

At the node 51 operating at a higher clock frequency, as shown in FIG.3B, the cycle offset value is continuously reset to zero twice, whichmeans a delay of one clock, resulting in time adjustment with a maximumadjusted amount of one clock. Since one clock is about 40 nanosecond,frequency fluctuations (variations in cycle time register value) of upto about 320 ppm will occur with respect to a period of 125 μsec.

The contents of the cycle time register is used for real-time transportof audiovisual stream (AV stream) defined by IEC 61883 standard. Toreceive the AV stream, it is necessary for a receiving side to decode itby faithfully reproducing the video frame frequency and audio samplingfrequency that were used at the transmitting side. However, thesemedia-dependent frequencies do not synchronize with frequencies used inthe IEEE1394 standard. To reproduce such frequency, the transmittingside transmits a packet of data attaching frequency information as atime stamp and the receiving side, when receiving the packet, looks atthis time stamp to reproduce the frequency information. The IEC61883standard defines that such time stamp information is determineddepending on the cycle time register of the transmitting side.

However, when frequency fluctuations, that is, variations in cycle timeregister value occur at the receiving side due to the synchronizationcontrol of cycle time register as described above, theAV-stream-dependent frequencies such as sampling timing also vary, whichadversely influences the quality of image and sound reproduced from thereceived AV stream. Therefore, an improved network synchronizationtechnique is desired.

Further, in the P1394.1 working group of IEEE, efforts are moving aheadto make IEEE1394 bridge standardization for connecting a plurality ofIEEE1394 buses to form a large network. In such a network environment,network-wide synchronization is needed to transfer real-time data overplural IEEE1394 buses, which will be described hereinafter withreference to FIG. 4.

As shown in FIG. 4, it is assumed that two bridges 70 and 71 connectthree IEEE1394 buses 90-92, in each of which synchronization control isperformed by a corresponding cycle master as described before. Sinceeach cycle master is operating at its own clock frequency, asynchronization method is needed among the cycle masters to achievenetwork-wide synchronization.

In FIG. 4, abridge has a plurality of portals, each of which isconnected to a corresponding IEEE1394 bus. For example, the bridge 70has portals 80 a and 80B each connected to IEEE1394 buses 90 and 91. TheIEEE1394 buses 90-92 have cycle masters 100-102 predetermined accordingto IEEE1394 standard. A portal may function as a cycle master because italso functions as an IEEE node. One of the cycle masters 100-102 isselected as a net cycle master that is a cycle master for the entirebridge network. Here, the cycle master 102 is designated as a net cyclemaster for the bridge network.

The other cycle masters 100 and 101 synchronize their own timeinformation to the time information of the net cycle master 102 usingthe following procedure.

First, the portal 81B of the bridge 71 synchronizes its own timeinformation to the net cycle master 102 using a cycle start packetreceived from the net cycle master 102. On the other hand, the otherportal 81A of the bridge 71 synchronizes its own time information to thecycle master 101 using a cycle start packet received from the cyclemaster 101. Accordingly, the bridge 71 can detect a time deviation ofthe cycle master 101 from the net cycle master 102 by comparing the timeinformation of the cycle master 101 to that of the net cycle master 102.When such a time deviation has been detected, the portal 81A transmits acontrol packet to the cycle master 101 to adjust the cycle time registerof the cycle master 101.

As shown in FIG. 5, a control packet, which is also called a cyclemaster adjustment packet, is formed according to a special isochronousstream packet format having no data field. Because of no data field, thevalue of a data length field is zero. A combination of tag and channelfields designates this packet as a control packet for cycle timeadjustment. Here, the tag and channel fields store “3” and “31”,respectively. A transaction code (tcode) field stores “10” to indicatethat this packet is based on the isochronous stream packet format.

A synchronization code (sy) field stores a value designating an amountto be adjusted in the cycle time register of a cycle master receivingthis packet. For example, when the synchronization code (sy) fieldstores a value of 1, a cycle master that has received the control packetelongates a period of the following isochronous cycle (125 μsec) by onecycle offset of about 40 nanoseconds. On the other hand, when thesynchronization code (sy) field stores a value of 3, a cycle master thathas received the control packet shortens a period of the followingisochronous cycle (125 μsec) by one cycle offset of about 40nanoseconds.

In this manner, the cycle master 101 can operate the bus 91 with theisochronous cycle synchronizing to that of the bus 92 connected to thenet cycle master 102. Therefore, the bus 91 synchronizes to the bus 92.Since the synchronization control for the bridge network is designed tosynchronize the isochronous cycle periods, the values of second countfield and cycle count field of a bus do not always coincide with thoseof another bus (see FIG. 2).

The bridge 70 performs the same synchronization control as the bridge71. The bus 90 synchronizes to the bus 91 that synchronizes the bus 92.Therefore, all the buses 90-92 synchronize. Such a synchronizationmethod is disclosed in Japanese Patent Application UnexaminedPublication Nos. P2000-307557A and P2000-32030A.

The synchronization control in the bridge network is performed byappropriately elongating or shortening a period of isochronous cycle(125 μsec) by one cycle offset of about 40 nanoseconds, resulting in aninstantaneous frequency fluctuation of approximately 320 ppm whenadjusted. In addition, the synchronization control in the bridge networkis performed by sequentially establishing synchronization from a bus tothe adjacent bus to synchronize all the buses. As described above,frequency fluctuations due to the above synchronization control ofisochronous cycle within an IEEE1394 bus or a bridge network composed ofa plurality of IEEE1394 buses adversely influence the quality oftransmission of a received real-time stream. Especially, in the case ofthe bridge network, frequency fluctuations may be accumulated every timethe synchronization control is performed for one bridge, resulting in alarge amount of frequency deviation. It is the same with othercommunication networks having a function of notifying time informationat regular intervals.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a networksynchronization method and system allowing reliable transmission systemby reducing frequency fluctuations of isochronous cycle due to thesynchronization control.

According to an aspect of the present invention, in a method forsynchronizing a plurality of devices connected to a network, wherein thedevices have time information individually varying in a predeterminedtime period of T, wherein a time master device that is one of thedevices periodically notifies its own time information as master timeinformation to time slave devices that are devices other than the timemaster device, said method includes the steps of: at each of the timeslave devices, preparing update-possible time points having a period ofT/N (N is an integer greater than 1); receiving the master timeinformation from the time master device; and updating its own timeinformation using the master time information at an update-possible timepoint just after the master time information has been received.

According to another aspect of the present invention, a network deviceconnected to a network, includes: a clock generator for generating aclock signal; a physical-layer circuit connected to the clock generator;and a link-layer circuit connected to the physical-layer circuit,wherein the link-layer circuit comprises: a timing generator forgenerating a first timing signal and a second timing signal from asystem clock signal inputted from the physical-layer circuit, whereinthe first timing signal is generated in a period of T and the secondtiming signal is generated at a time point corresponding to a period ofT/N (N is an integer greater than 1); a time information memory forstoring time information, which varies according to the first timingsignal; and a controller controlling the time information memory suchthat, when receiving reference time information from the network, thetime information stored in the time information memory is updated usingthe reference time information at a time point according to the secondtiming signal just after the reference time information has beenreceived.

The timing generator may include: a frequency divider for dividing thesystem clock signal in frequency by two to produce the first timingsignal having the period of T; and a frequency multiplier formultiplying the system clock signal in frequency by two to produce thesecond timing signal having a period of T/2.

The timing generator may include: a frequency multiplier for multiplyingthe system clock signal in frequency by two to produce a timing signalhaving a period of T/2; and a base-4 counter for counting from 0 to 3according to the timing signal to produce the first timing signal everytime the base-4 counter is reset to 0, wherein, when the reference timeinformation has been received, the base-4 counter is reset to 0 togenerate the second timing signal.

The timing generator may include: a binary counter for countingaccording to the system clock signal to produce the first timing signalevery time the binary counter is reset to 0, wherein, when the referencetime information has been received, the binary counter is reset to 0 togenerate the second timing signal.

According to still another aspect of the present invention, a bridgeconnecting a plurality of networks, each of which individually has timeinformation varying in a predetermined time period of T, includes: afirst portal connected to a first network having first time information;a second portal connected to a second network having second timeinformation; a time difference detector for detecting a time differenceof the second time information with respect to the first timeinformation; an adjustment value generator for producing a timeadjustment value based on the time difference, wherein the timeadjustment value is an integral multiple of T/M (M is an integer greaterthan 1); and a controller adjusting the second time information for thesecond network by the time adjustment value.

The adjustment value generator may include: a table containing apredetermined correspondence between time differences and timeadjustment values, wherein the time adjustment values have apredetermined step of adjustment and an absolute value of a timeadjustment value is restricted within a predetermined range, wherein theadjustment value generator produces a time adjustment valuecorresponding to the time difference by referring to the table.

A maximum absolute value of the time adjustment values may be a minimumvalue of integral multiples of the predetermined step of adjustmentsufficient for adjusting a largest one of frequency deviations in localclocks of the network.

When an absolute value of the time difference exceeds a predeterminedthreshold, the time adjustment value may be set to a predetermined valuebeyond the predetermined range.

According to further aspect of the present invention, in a method forsynchronizing a bridge network composed of at least one bridge having aplurality of portals each connected to different networks, each of whichincludes at least one node, wherein each of the portals and networksindividually has a clock generator by which time information varies in apredetermined time period of T, wherein one of the portals is a masterportal and the others are slave portals, said method includes the stepsof: a) detecting a time difference of slave time information of eachslave portal with respect to master time information of the masterportal; b) producing a time adjustment value based on the timedifference, wherein the time adjustment value is an integral multiple ofT/M (M is an integer greater than 1); and c) adjusting the slave timeinformation by the time adjustment value.

According to furthermore aspect of the present invention, in a methodfor synchronizing a bridge network composed of at least one bridgehaving a plurality of portals each connected to different networks, eachof which includes at least one node, wherein each of the portals andnetworks individually has a clock generator by which time informationvaries in a predetermined time period of T, wherein one of the portalsis a master portal and the others are slave portals, said methodincludes the steps of: a) each of portals detecting a lowest clockaccuracy in a corresponding network; b) dynamically determining amaximum adjustment value based on a network-wide lowest clock accuracyselected from lowest clock accuracies detected by the portals; c)detecting a time difference of slave time information of each slaveportal with respect to master time information of the master portal; d)producing a time adjustment value within the dynamically determinedmaximum adjustment value based on the time difference, wherein the timeadjustment value is an integral multiple of T/M (M is an integer greaterthan 1); and e) adjusting the slave time information by the timeadjustment value.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an IEEE1394 network for explainingdata transport in conformity with the IEEE 1394 standard;

FIG. 2 is a diagram showing the format of a cycle time register providedin a node of the IEEE1394 network;

FIG. 3A is a timing chart showing a cycle start packet transmissionoperation of a cycle master in the IEEE1394 network;

FIG. 3B is a timing chart showing an example of time informationsynchronization control of a node in the IEEE1394 network;

FIG. 3C is a timing chart showing another example of time informationsynchronization control of a node in the IEEE1394 network;

FIG. 4 is a block diagram showing an IEEE1394 bridge network forexplaining synchronization control;

FIG. 5 a diagram showing the format of a control packet for cycle timeregister adjustment employed in the IEEE1394 bridge network;

FIG. 6 is a block diagram showing a related internal circuit of anIEEE1394 link-layer LSI according to a first embodiment of the presentinvention;

FIG. 7 is a timing chart showing an operation of cycle time registercontrol in the IEEE1394 link-layer LSI according to the firstembodiment;

FIG. 8 is a flow chart showing a main operation of the IEEE1394link-layer LSI according to the first embodiment;

FIG. 9 is a block diagram showing another example of the IEEE1394link-layer LSI according to the first embodiment of the presentinvention;

FIG. 10 is a timing chart showing an operation of cycle time registercontrol in the IEEE1394 link-layer LSI of FIG. 9;

FIG. 11 is a block diagram showing an internal circuit of a digitalvideo player employing an IEEE1394 link-layer LSI according to a secondembodiment of the present invention;

FIG. 12 is a block diagram showing an internal circuit of the IEEE1394link-layer LSI according to the second embodiment;

FIG. 13 is a timing chart showing an operation of cycle time registercontrol in the IEEE1394 link-layer LSI according to the secondembodiment;

FIG. 14 is a flow chart showing a main operation of the IEEE1394link-layer LSI according to the second embodiment;

FIG. 15 is a block diagram showing an IEEE1394 bridge network employinga bridge according to a third embodiment of the present invention;

FIG. 16 is a block diagram showing an inter-bus synchronization controlcircuit of the bridge according to the third embodiment;

FIG. 17A is a timing chart showing an operation of inter-bussynchronization control in one portal of the bridge as shown in FIG. 16;

FIG. 17B is a timing chart showing an operation of inter-bussynchronization control in the other portal of the bridge as shown inFIG. 16;

FIG. 18 is a block diagram showing an internal circuit of a bridgeaccording to a fourth embodiment of the present invention;

FIG. 19A is a timing chart showing an operation of inter-bussynchronization control in one portal of the bridge as shown in FIG. 18;

FIG. 19B is a timing chart showing an operation of inter-bussynchronization control in the other portal of the bridge as shown inFIG. 18;

FIG. 20 is a flow chart showing a schematic example of an operation ofthe other portal of the bridge as shown in FIG. 18;

FIG. 21 is a block diagram showing an IEEE1394 bridge network employinga bridge according to a fifth embodiment of the present invention; and

FIG. 22 is a block diagram showing the bridge according to the fifthembodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, preferred embodiments of the present invention will bedescribed in detail with reference to the drawings.

First Embodiment

The overwriting of the cycle time register provided in a network devicewill be described when a cycle start packet has been received from acycle master.

1.1) Link-Layer LSI

Referring to FIG. 6, a 1394 link-layer LSI 20A is employed in a node of,for example, the IEEE1394 network as shown in FIG. 1. The 1394link-layer LSI 20A is provided with a physical-layer/link-layer(PHY/LINK) interface 110 through which plural signals (e.g. in theneighborhood of nine kinds of signals) are inputted and outputted fromand to the PHY LSI. In FIG. 6, however, only a system clock signal SCLKand data are depicted. The system clock signal SCLK is received from thePHY LSI. As for data, the PHY/LINK interface 110 is a bidirectionalinterface to the PHY LSI to exchange packets.

The 1394 link-layer LSI 20A operates according to the system clocksignal SCLK, which has a frequency fs of 49.152 MHz, that is, two timesthe clock frequency of the crystal oscillator provided in the PHY LSI(see FIG. 1). The bit rate per data signal line is 49.152 Mbps. S100,S200 and S400 data are transferred using two signal lines, four signallines, and eight signal lines, respectively. The cycle start packet istransferred in S100 and therefore two signal lines are used to receiveit from the PHY LSI.

The system clock signal SCLK is output to a frequency divider 120, afrequency multiplier 130, and a packet receiver 140. The frequencydivider 120 divides the frequency fs of the system clock signal SCLK bytwo to produce a fs/2 clock of 24.576 MHz, which is supplied to a cycletime register controller 150. The frequency multiplier 130 multipliesthe frequency fs of the system clock signal SCLK by two to produce a 2fs clock of 98.304 MHz, which is supplied to the cycle time registercontroller 150.

The PHY/LINK interface 110 converts a received packet of data into a32-bit parallel signal and outputs it to the packet receiver 140. Thepacket receiver 140 performs bit-error check and packet type check ofthe input packet according to the system clock signal SCLK anddistributes it to destinations depending on the packet type. Here, onlythe cycle time register controller 150 is depicted as one destination.When receiving the cycle start packet, the packet receiver 140 outputstime information included in the received cycle start packet to thecycle time register controller 150.

The cycle time register controller 150 is a functional block thatcontrols the value of the cycle time register depending on the timeinformation inputted from the packet receiver 140 and the ½ fs clock andthe 2 fs clock from respective ones of the frequency divider 120 and thefrequency multiplier 130.

The internal circuit of the 1394 link-layer LSI 20A is integrated in acircuit block. In FIG. 6, only blocks related to the present inventionare depicted for the sake of simplicity.

1.2) Cycle Time Register Control

Referring to FIG. 7, the cycle time register controller 150 incrementsthe cycle offset value of the cycle time register at the rising edge ofthe ½ fs clock and overwrites the cycle offset value with the input timeinformation at timing of the rising edge of the 2 fs clock. For example,when a cycle start packet having a cycle offset value of “34” as timeinformation is received at the timing as indicated by an arrow, theoverwriting of the cycle offset value with “34” is performed at therising edge of the 2 fs clock immediately after the receipt of the cyclestart packet. At the rising edge of the ½ fs clock immediately afterthat, the cycle offset value is incremented to “35”.

In this manner, the cycle time register can be adjusted with aresolution of about 10 nanoseconds. This allows much more accurate timeadjustment to the cycle master, compared to the conventional one-cycleoffset adjustment (in steps of about 40 nanoseconds). Accordingly, theisochronous cycle period of about 125 μsec can be adjusted moreprecisely, resulting in reduced frequency fluctuations at each node.

1.3) Operation

Referring to FIG. 8, it is determined whether a cycle start packet isreceived (step S101). When no cycle start packet is received (NO in stepS101), it is determined whether the present timing is coincident to therising edge of the ½ fs clock (step S102). At the rising edge of the ½fs clock (YES in step S102), it is further determined whether the cycleoffset value is equal to “3071” (step S103). When it is not equal to“3071” (NO in step S103), the cycle offset value is incremented by one(step S104) and the control goes back to the step S101. When it is equalto “3071” (YES in step S103), the cycle count value of the cycle timeregister is incremented by one and resets the cycle offset value to zero(step S105). Thereafter, the control goes back to the step S101.

When a cycle start packet is received (YES in step S101), it isdetermined whether the present timing is coincident to the rising edgeof the 2 fs clock (step S106). At the rising edge of the 2 fs clock (YESin step S106), the existing cycle offset value is overwritten with thetime information included in the received cycle start packet (stepS107). Thereafter, the control goes back to the step S101.

1.4) Modified Example

Referring to FIG. 9, a link-layer LSI 20B according to a modifiedexample of the first embodiment is provided with a base-4 counter 160instead of the frequency divider 120. The other circuit blocks are thesame as those in the link-layer LSI 20A of FIG. 6. Accordingly, theseblocks are denoted by the same reference numerals and the details willbe omitted.

The base-4 counter 160 increments by one from 0 to 3 before resetting tozero and starting again and is forced to be reset to zero when thepacket receiver 140 outputs time information included in a receivedcycle start packet. The base-4 counter 160, when reset to zero, outputsa pulse signal to the cycle time register controller 150.

As shown in FIG. 10, the base-4 counter 160 increments by one from 0 to3 according to the 2 fs clock received from the frequency multiplier 130and outputs the pulse signal to the cycle time register controller 150when it is reset to zero (see FIG. 10(g)). The cycle time registercontroller 150 increments the cycle offset value of the cycle timeregister when the pulse signal is received from the base-4 counter 160.

When a cycle start packet is received and its time information is outputto the cycle time register controller 150, the base-4 counter 160 isforced to be reset to zero, which causes the pulse signal to be outputto the cycle time register controller 150. When the pulse signal isreceived, the cycle time register controller 150 overwrites the cycleoffset value with the time information received from the packet receiver140.

For example, when a cycle start packet having a cycle offset value of“34” as time information is received at the timing as indicated by anarrow, the base-4 counter 160 is forced to be reset to zero, whichcauses the pulse signal to be output to the cycle time registercontroller 150. Accordingly, the overwriting of the cycle offset valuewith “34” is performed at the rising edge of the 2 fs clock immediatelyafter the receipt of the cycle start packet. At the rising edge of apulse signal immediately after that, the cycle offset value is increasedto “35”.

In this manner, concurrently with the overwriting of the cycle offsetvalue with the received time information, the base-4 counter 160 isforced to be reset to zero. Therefore, the overwritten cycle offsetvalue is surely held for a lapse of one cycle offset period after theoverwriting.

This modified example employing the base-4 counter 160 uses only oneclock (2 fs clock), resulting in further stable operation at each node.In addition, as described before, frequency fluctuations can beeffectively reduced. The cycle time register can be adjusted with aresolution of about 10 nanoseconds. This allows much more accurate timeadjustment to the cycle master, compared to the conventional one-cycleoffset adjustment (in steps of about 40 nanoseconds). Accordingly, theisochronous cycle period of about 125 μsec can be adjusted moreprecisely, resulting in reduced frequency fluctuations at each node.

Further, in place of the frequency multiplier 130 of 2-fold increase infrequency, an n-fold frequency multiplier (n=4, 8, or other number) maybe used to obtain a higher resolution.

Second Embodiment

2.1) Digital Video Player

Referring to FIG. 11, a digital video player 220 employs a link-layerLSI 20C according to a second embodiment of the present invention. Thedigital video player 220 further includes a PHY LSI 10, a processor(CPU) 170, a ROM 180, RAM 190, a decoder 200, and a digital-to-analogconverter 210. The digital video player 220 decodes a digital videosignal of DV format received from the IEEE1394 bus and outputs an analogvideo signal.

The digital video signal of DV format is mapped into isochronous streampacket following IEC 61883 standard. More specifically, the upper eightbytes of the data field of an isochronous stream packets are defined asa header of a common isochronous packet (CIP) in the IEC 61883 standard.The type of video format and time stamp information are stored in theCIP header.

The link-layer LSI 20C has a host interface to a host bus connected toother components including the processor (CPU) 170 and a streaminterface to the decoder 200 for input and output of isochronous streampackets which are needed to be processed at high speeds. The processor170 performs software processing of IEEE1394 protocols of transactionlayer and the like. The decoder 200 also has a host interface and astream interface similar to those of the link-layer LSI 20C.

2.1) Link-Layer LSI

Referring to FIG. 12, the link-layer LSI 20C is provided with aphysical-layer/link-layer (PHY/LINK) interface 110 through which pluralsignals (e.g. in the neighborhood of nine kinds of signals) are inputtedand outputted from and to the PHY LSI 10. In FIG. 12, however, only asystem clock signal SCLK and data are depicted. The system clock signalSCLK is received from the PHY LSI 10. As for data, the PHY/LINKinterface 110 is a bidirectional interface to the PHY LSI 10 to exchangepackets.

The 1394 link-layer LSI 20C operates according to the system clocksignal SCLK, which has a frequency fs of 49.152 MHz, that is, two timesthe clock frequency of the crystal oscillator provided in the PHY LSI10. A packet inputted from the IEEE1394 bus enters a packet receiver 140through the PHY/LINK interface 110. When the packet receiver 140determines that the input packet is an isochronous stream packet, thepacket of data is output to an IEC61883 termination 240. In addition,when receiving a cycle start packet, the packet receiver 140 outputstime information included in the cycle start packet to a cycle timeregister controller 150.

The IEC61883 termination 240 reconstructs DV data based on informationstored in the CIP header and produces a nominal video frame pulse ofapproximate 30 Hz from the time stamp stored in the CIP header and timeinformation inputted from the cycle time register of its own and outputsthem to the stream interface.

The 1394 link-layer LSI 20C performs cycle time register control using abinary counter 230 that operates according to the system clock signalSCLK. The binary counter 230 alternately indicates ‘0’ and ‘1’ and isforced to be reset to zero when a cycle start packet is received. Thebinary counter 230 outputs a pulse signal when the binary counter 230indicates zero. The cycle time register controller 150 performs thecycle time register control using the output of the binary counter 230,the system clock signal SCLK, and a received cycle start packet, whichwill be described with reference to FIG. 13.

2.3) Cycle Time Register Control

Referring to FIG. 13, the binary counter 230 outputs the pulse signal tothe cycle time register controller 150 when it is reset to zero (seeFIG. 13(k)). The cycle time register controller 150 increments the cycleoffset value of the cycle time register when the pulse signal isreceived from the binary counter 230.

When a cycle start packet is received and its time information is outputto the cycle time register controller 150, the binary counter 230 isforced to be reset to zero, which causes the pulse signal to be outputto the cycle time register controller 150. When the pulse signal isreceived, the cycle time register controller 150 overwrites the cycleoffset value with the time information received from the packet receiver140.

For example, when a cycle start packet having a cycle offset value of“35” as time information is received at the timing as indicated by anarrow, the binary counter 230 is forced to be reset to zero, whichcauses the pulse signal to be output to the cycle time registercontroller 150. Accordingly, the overwriting of the cycle offset valuewith “35” is performed at the rising edge of the system clock signalSCLK immediately after the receipt of the cycle start packet. At therising edge of a pulse signal immediately after that, the cycle offsetvalue is increased to “36”.

In this manner, concurrently with the overwriting of the cycle offsetvalue with the received time information, the binary counter 230 isforced to be reset to zero. Therefore, the overwritten cycle offsetvalue is held for a lapse of one cycle offset period after theoverwriting.

Referring to FIG. 14, it is determined whether the system clock signalSCLK goes high (step S201) and, at the rising edge of the system clocksignal SCLK (YES in step S201), it is further determined whether a cyclestart packet has been received (step S202). When no cycle start packetis received (NO in step S202), it is determined whether the binarycounter 230 is equal to 0 (step S203).

When the binary counter 230 is not equal to 0, that is, 1 (NO in stepS203), the binary counter 230 is reset to 0 (step S204) and the controlgoes back to the step S201. When the binary counter 230 is equal to 0(YES in step S203), it is further determined whether the cycle offsetvalue is equal to “3071” (step S205).

When it is not equal to “3071” (NO in step S205), the cycle offset valueis incremented by one (step S206). When it is equal to “3071” (YES instep S205), the cycle count value of the cycle time register isincremented by one and resets the cycle offset value to zero (stepS208). After the step S206 or S208, the binary counter 230 is set to 1(step S207) and the control goes back to the step S201.

When a cycle start packet is received (YES in step S202), the binarycounter 230 is reset to 0 (step S209) and the existing cycle offsetvalue is overwritten with the time information included in the receivedcycle start packet (step S210). Thereafter, the control goes back to thestep S201.

In this manner, much more accurate time adjustment to the cycle mastercan be achieved, compared to the conventional one-cycle offsetadjustment. Accordingly, the isochronous cycle period of about 125 μseccan be adjusted more precisely, resulting in reduced frequencyfluctuations, which achieves reduced jitter of the frame pulse signal.Therefore, the digital video player 220 can decode a high-quality videosignal.

The second embodiment as shown in FIG. 12 employs no frequencymultiplier, resulting in a more simplified circuit structure.

In this embodiment, the cycle time register control is performed by thecycle time register controller 150 provided in the link-layer LSI 20C.Alternatively, it is possible to perform the same control by running acycle time register control program on the processor 170. The cycle timeregister control program may be previously stored in the ROM 180.

Third Embodiment

3.1) Bridge Network

Referring to FIG. 15, it is assumed that a bridge 70A connects twoIEEE1394 buses 90 and 91 and the bridge 70A is composed of portals 80Aand 80B, which are connected to the buses 90 and 91, respectively. Therespective buses 90 and 91 are connected to nodes 50 and 51.

In this embodiment, the node 50 functions as a cycle master of the bus90 and a net cycle master for the entire bridge network. On the otherhand, the portal 80B of the bridge 70A functions as a cycle master ofthe bus 91. Therefore, the bridge 70A performs synchronization of theportal 80B to the portal 80A. The portal 80A is a master portal and theportal 80B is a slave portal. The slave portal 80B as the cycle masterof the bus 91 notifies the bus 91 by a cycle start packet of timeinformation obtained by the cycle time register control, so thatsynchronization is established in the entire bridge network.

3.2) Bridge

Referring to FIG. 16, the bridge 70A includes an inter-bussynchronization control circuit composed of the master portal 80A andthe slave portal 80B. The master portal 80A includes a cycle timeregister controller 150A. The slave portal 80 b includes a frequencymultiplier 130, a cycle time register controller 150B, an error detector260, and an adjustment value generator 270.

In the master portal 80A, the cycle time register controller 150Asynchronizes to the net cycle master 50 according to an appropriatesynchronization control as described before. Every time a cycle offsetvalue (cycle_offset) of the cycle time register incorporated in themaster portal 80A is coincident to a predetermined value, the cycle timeregister controller 150A outputs a sync pulse to the error detector 260of the slave portal 80B. For example, the predetermined value may be setto 3070. In this case, every time cycle_offset=3070, the sync pulse isgenerated.

In the slave portal 80B, the error detector 260 operates according to a2 fs clock signal of 98.304 MHz, which is generated by the frequencymultiplier 130. The frequency multiplier 130 multiplies the frequency fsof the system clock signal SCLK by two to produce the 2 fs clock of98.304 MHz, which is supplied to the error detector 260 and a cycle timeregister controller 150B.

3.2.1) Error Detector

The error detector 260 has a base-4 counter incorporated therein. Byusing the base-4 counter, the error detector 260 can detect an errorfrom the net cycle master with a resolution of about 10 nanoseconds,which is one-fourth of one cycle offset of about 40 nanoseconds.

When having received the sync pulse from the cycle time registercontroller 150A, the error detector 260 inputs a cycle offset value ofthe cycle time register incorporated in the cycle time registercontroller 150B. Then, the predetermined value (here, 3070) issubtracted from the cycle offset value of the slave portal 80B toproduce a cycle offset error of the slave portal 80 b with respect tothe master portal 80A. A detected error cycle is obtained by adding thecycle offset error to one-fourth of a value of the base-4 counter atthat time point. An example of time adjustment will be described withreference to FIGS. 17A and 17B.

3.2.2) Time Adjustment

Referring to FIG. 17A, as described before, when a cycle offset value(cycle_offset) of the cycle time register incorporated in the masterportal 80A is coincident to “3070”, the cycle time register controller150A outputs a sync pulse to the error detector 260 of the slave portal80B.

Referring to FIG. 17B, it is assumed that the sync pulse is receivedfrom the cycle time register controller 150A when the base-4 counter ofthe error detector 260 indicates “2” and its own cycle offset value ofthe cycle time register is “3069”. In this case, a cycle offset error is−1, which is obtained by subtracting 3070 from 3069. Since the base-4counter indicates “2”, a detected error cycle is −½, which is obtainedby adding 2/4 to −1. This means that the cycle offset of the slaveportal 80B lags that of the master portal 80A by ½ cycle.

The adjustment value generator 270 generates a cycle period timeadjustment value in the slave portal 80B based on the detected errorcycle inputted from the error detector 260, which will be described indetail later. The cycle time register controller 150B inputs the cycleperiod time adjustment value from the adjustment value generator 270 andincreases or decreases a cycle period of 125 μsec by the cycle periodtime adjustment value. This cycle period time adjustment value is alsodetermined with a resolution of one-fourth of one cycle offset. Sincethe portal 80B is a cycle master for the bus 91, the portal 80Btransmits a cycle start packet depending on the adjusted timing, so thatthe buses 90 and 91 are synchronized.

3.2.3) Adjustment Value

In the adjustment value generator 270, a relationship between inputcycle errors and output adjustment values is determined as describedhereinafter.

The maximum absolute value of an adjustment value is determined based onthe poorest clock frequency accuracy in the bridge network as describedbelow. Since the IEEE1394 standard defines that the clock frequencyaccuracy is ±100 ppm, the worst imaginable case is a frequency deviationof 200 ppm. When an isochronous cycle that is a cycle offset of 3072 isincreased or decreased by an amount of ¼-cycle offset as an adjustmentvalue, a frequency deviation is approximately 81.4 ppm (=0.25/3072).Accordingly, when a frequency deviation of 200 ppm occurs as the worstcase, the adjustment value of ¼-cycle offset cannot control such afrequency deviation. To effectively control a frequency deviation of 200ppm, an adjustment value of at least ¾-cycle offset is needed in thecase of a ¼-cycle offset resolution. This adjustment value can controlup to a frequency deviation of approximately 244.1 ppm (=0.75/3072).Accordingly, the ¾-cycle offset is used as the maximum adjustment valueand the relationship between errors and adjustment values is shown, asan example, in TABLE I. TABLE I Absolute value of error Adjustment value¾-cycle offset or more ¾-cycle offset ½-cycle offset ½-cycle offset¼-cycle offset ¼-cycle offset  0-cycle offset  0-cycle offset

Another relationship may be possible. For example, when the absolutevalue of error is equal to or lower than ½-cycle offset, the adjustmentvalue may be set to 0 regardless of absolute values of error.Alternatively, the adjustment value may be set based on a history ofadjustment values or so-called integral control.

Further, in the case of an extremely large error when the cycle timeregister is in pull-in status just after the bridge is powered on, anadjustment value much larger than the clock frequency accuracy may beused to rapidly establish synchronization. For example, when theabsolute value of error is greater than 100-cycle offset, the adjustmentvalue is set to 32-cycle offset.

In this manner, much more accurate time adjustment of the slave portal80B to the master portal 80A can be achieved with a resolution ofapproximately 10 nanoseconds, compared to the conventional one-cycleoffset (approximately 40 nanoseconds). Accordingly, frequencyfluctuations or deviations of the cycle time register can be reduced inthe IEEE1394 bus 91 having the portal 80B as a cycle master.

In FIG. 15, another node may be a cycle master of the bus 91. Forexample, instead of the portal 80B, a node 51 may be the cycle master.In this case, the functions defined in P1394.1 standard as describedbefore is needed in the portal 80B and the node 51. However, theadjustment value of P1394.1 standard is fixed to ±1-cycle offset.Accordingly, the synchronization code (sy) field is necessarily definedso as to allow a higher resolution of adjustment.

Fourth Embodiment

4.1) Bridge Network

A bridge network employing a bridge according to a fourth embodiment ofthe present invention is similar to that of the third embodiment asshown in FIG. 15. In the fourth embodiment, it is also assumed that abridge 70A connects two IEEE1394 buses 90 and 91 and the bridge 70A iscomposed of portals 80A and 80B, which are connected to the buses 90 and91, respectively. The respective buses 90 and 91 are connected to nodes50 and 51.

In this embodiment, the node 50 functions as a cycle master of the bus90 and a net cycle master for the entire bridge network. On the otherhand, the portal 80B of the bridge 70A functions as a cycle master ofthe bus 91. Therefore, the bridge 70A performs synchronization of theportal 80B to the portal BOA. The portal 80A is a master portal and theportal BOB is a slave portal. The slave portal 80B as the cycle masterof the bus 91 notifies the bus 91 by a cycle start packet of timeinformation obtained by the cycle time register control, so thatsynchronization is established in the entire bridge network.

4.2) Bridge

Referring to FIG. 18, the bridge 70A includes an inter-bussynchronization control circuit composed of the master portal 80A andthe slave portal BOB. The master portal 80A includes a cycle timeregister controller 150A and a binary counter 230. The slave portal 80 bincludes a cycle time register controller 150B, an error detector 260,and an adjustment value generator 270.

In the master portal 80A, the cycle time register controller 150Asynchronizes to the net cycle master 50 by receiving a cycle startpacket from the net cycle master with a resolution of the system clocksystem SCLK, which is employed in the second embodiment (see FIGS. 12and 13). More specifically, the binary counter 230 operates according tothe system clock signal SCLK and outputs a pulse to the cycle timeregister controller 150A every time its count is equal to 0. Further,the binary counter 230 is reset to zero when the cycle start packet hasbeen received. The cycle offset value of the cycle time registerincorporated in the cycle time register controller 150A is incrementedby one according to the output of the binary counter 230. Every time thecycle offset value (cycle_offset) of the cycle time register iscoincident to a predetermined value (here, 3070), the cycle timeregister controller 150A outputs a sync pulse to the error detector 260of the slave portal 80B. In this manner, the synchronization control ofthe cycle time register is performed with a resolution of the systemclock signal SCLK, resulting in reduced frequency deviations of thecycle time register.

In the slave portal 80B, the system clock signal SCLK is supplied to theerror detector 260 and a cycle time register controller 150. The errordetector 260 operates according to the system clock signal SCLK. Whenhaving received the sync pulse from the cycle time register controller150A, the error detector 260 inputs a cycle offset value of the cycletime register incorporated in the cycle time register controller 150B.Then, the predetermined value (here, 3070) is subtracted from the cycleoffset value of the slave portal 80B to produce a cycle offset error ofthe slave portal 80B with respect to the master portal 80A. An exampleof time adjustment will be described with reference to FIGS. 19A and19B.

4.3) Time Adjustment

Referring to FIG. 19A, as described before, when a cycle offset value(cycle_offset) of the cycle time register incorporated in the masterportal 80A is coincident to “3070”, the cycle time register controller150A outputs a sync pulse to the error detector 260 of the slave portal80B.

Referring to FIG. 19B, it is assumed that the sync pulse is receivedfrom the cycle time register controller 150A when its own cycle offsetvalue of the cycle time register is “3071”. In this case, a cycle offseterror is +1, which is obtained by subtracting 3070 from 3071. This meansthat the cycle offset of the slave portal 80B leads that of the masterportal 80A by one cycle.

The adjustment value generator 270 generates a cycle period timeadjustment value in the slave portal 80B based on the detected errorcycle and a predetermined correspondence table. Here, the one-cycleoffset is used as the maximum adjustment value and the relationshipbetween errors and adjustment values is shown, as an example, in TABLEII. TABLE II Absolute value of error Adjustment value 2-cycle offset ormore 1-cycle offset 1-cycle offset ½-cycle offset  0-cycle offset0-cycle offset

Accordingly, when the cycle offset error is +1, the adjustment valuegenerator 270 generates a cycle period time adjustment value of +½-cycleoffset. The cycle time register controller 150B inputs the cycle periodtime adjustment value of +½-cycle offset and increases a cycle period of125 μsec by ½-cycle offset as shown in FIG. 19B. Since the portal 80B isa cycle master for the bus 91, the portal 80B transmits a cycle startpacket depending on the adjusted timing, so that the buses 90 and 91 aresynchronized.

4.4) Operation of Slave Portal

Referring to FIG. 20, it is determined whether the system clock signalSCLK goes high (step S301) and, at the rising edge of the system clocksignal SCLK (YES in step S301), it is further determined whether a syncpulse has been received (step S302). When no sync pulse is received (NOin step S302), normal cycle offset processing is performed (step S306)and the control goes back to the step S301.

When a sync pulse has been received (YES in step S302), the errordetector 260 subtracts the predetermined value (here, 3070) from thecycle offset value of the slave portal 80B to produce a difference incycle offset of the slave portal 80B with respect to the master portal80A (step S303).

The adjustment value generator 270 generates a cycle period timeadjustment value in the slave portal 80B based on the calculateddifference and the correspondence table (TABLE II) and the cycle timeregister controller 150B changes the cycle period by the cycle periodtime adjustment value (step S305).

In this manner, much more accurate time adjustment of the slave portal80B to the master portal 80A can be achieved. Accordingly, frequencyfluctuations or deviations of the cycle time register can be reduced inthe IEEE1394 bus 91 having the portal 80B as a cycle master.

Fifth Embodiment

Referring to FIG. 21, a bridge 70B according to a fifth embodiment ofthe present invention has three or more portals, each of which isconnected to a corresponding IEEE1394 bus. In this example, the bridge70B is provided with four portals 80A-80D each having buses 90-93connected thereto, and it is assumed that each portal is a cycle masterfor a corresponding bus and the portal 80A functions as the net cyclemaster.

Referring to FIG. 22, the bridge 70B is functionally divided into themaster portal 80A and other slave portals 80B-80D. Every time a cycleoffset value (cycle_offset) of the cycle time register incorporated inthe master portal 80A is coincident to “3070”, the cycle time registercontroller 150A outputs a sync pulse to the slave portals 80B-80D. Theslave portals 80B-80D individually perform synchronization control basedon the sync pulse received from the master portal 80A. Thesynchronization control in each slave portal is basically the same asthat in the fourth embodiment (see FIG. 18) but it is different from thefourth embodiment in a function of dynamically determining the maximumadjustment value. Details of this function will be described below.

IEEE1394 standard, as described before, defines that the permissibledeviation of a clock frequency is ±100 ppm. However, if the clockfrequency of each network device is actually more precise, then theadjustment value for synchronization control is expected to be smaller,resulting in improved synchronization performance. Accordingly, themaximum adjustment value can be dynamically determined depending on theclock frequency accuracy of devices actually connected to the network.The bridge 70B according to the present embodiment implements such afunction of dynamically determining the maximum adjustment value.

As shown in FIG. 22, the master portal 80A is provided with a clockfrequency accuracy investigator 280A and a maximum adjustment valuedecision section 290. The respective slave portals 80B-80D are providedwith clock frequency accuracy investigators 280B-280D. Each of the clockfrequency accuracy investigators 280A-280D investigates the clockfrequency accuracy of a node connected to a corresponding bus. Morespecifically, the clock frequency accuracy information has been writtenin the cyc_clk_acc field of a configuration ROM area where nodeperformance information has been stored. It is enough to read the clockfrequency accuracy information from a portal and a cycle master within acorresponding bus. When there is a possibility that its cycle masterchanges depending on insertion or removal of a node, it is necessary toupdate the investigation result as occasion demands.

The cyc_clk_acc values of all nodes may be investigated regardless ofnode type such as portal or cycle master. However, the cyc_clk_acc fieldimplementation is not necessary. Therefore, even if a read request issent to all nodes, a node having no cyc_clk_acc field implemented cannotrespond to the read request. In reality, almost all nodes having thecycle master function are expected to have the cyc_clk_acc fieldimplemented. Accordingly, this cyc_clk_acc value reading procedure canbe effectively used.

After clock frequency accuracy information have been read from nodesconnected to a bus, the clock frequency accuracy investigator of acorresponding slave portal detects the lowest one of the read clockfrequency accuracies and outputs it to the maximum adjustment valuedecision section 290 of the master portal 80A. The maximum adjustmentvalue decision section 290 detects the network-wide lowest one of thelowest clock frequency accuracies received from the slave portals80B-80D and determines the maximum adjustment value based on thenetwork-wide lowest clock frequency accuracy.

Specifically, the maximum adjustment value is calculated as k·paccording to the following inequality:k·p/3072>=2·acc _(—) max,where p is a time resolution of synchronization control (cycle offset)and acc_max is the lowest clock frequency accuracy.

For example, in the case where synchronization control is performed witha time resolution of ¼ cycle offset (p=¼), when the clock frequencyaccuracy is 100 ppm or less, k=3 and therefore the maximum adjustmentvalue is k·p=¾ (cycle offset). In the case of an environment that theclock frequency accuracy is 20 ppm or less, the maximum adjustment valuecan be suppressed to ¼ cycle offset.

After the maximum adjustment value has been determined like this, themaximum adjustment value decision section 290 outputs it to theadjustment value generators 270B-270D of the slave portals 80 b-80D.Using the maximum adjustment value, each of the slave portals 80 b-80Dperforms the synchronization control as described before.

In the above example, each portal investigates the clock frequencyaccuracy of a node connected to the corresponding bus. Alternatively,one or more predetermined node may investigate the clock frequencyaccuracy of a node connected to another bus that is not connected to thepredetermined node.

Further, in the above example, the investigation result of clockfrequency accuracy for each bus is reported to the master portal 80A andthe maximum adjustment value obtained from the investigation result isnotified to all slave portals 80B-80D. This dynamically adjustment valuedetermination operation is completely performed within the bridge 70B.However, it can be performed over a plurality of bridges by anadditional protocol such as a new message format to exchange informationbetween IEEE1394 buses.

The present invention is not restricted to the case of IEEE1394standard. As long as time information is notified at regular intervalsto synchronize a plurality of network devices, the present invention canbe applied to such a system.

As described above, according to the present invention, frequencyfluctuations caused by time information synchronization in a network canbe reduced, resulting in improved quality of transmission of real-timedata such as audiovisual stream through the network.

1. A network device connected to a network, comprising: a clockgenerator for generating a clock signal; a physical-layer circuitconnected to the clock generator; and a link-layer circuit connected tothe physical-layer circuit, wherein the link-layer circuit comprises: atiming generator for generating a first timing signal and a secondtiming signal from a system clock signal inputted from thephysical-layer circuit, wherein the first timing signal is generated ina period of T and the second timing signal is generated at a time pointcorresponding to a period of T/N (N is an integer greater than 1); atime information memory for storing time information, which variesaccording to the first timing signal; and a controller controlling thetime information memory such that, when receiving reference timeinformation from the network, the time information stored in the timeinformation memory is updated using the reference time information at atime point according to the second timing signal just after thereference time information has been received.
 2. The network deviceaccording to claim 1, wherein the timing generator comprises: afrequency divider for dividing the system clock signal in frequency bytwo to produce the first timing signal having the period of T; and afrequency multiplier for multiplying the system clock signal infrequency by two to produce the second timing signal having a period ofT/2.
 3. The network device according to claim 1, wherein the timinggenerator comprises: a frequency multiplier for multiplying the systemclock signal in frequency by two to produce a timing signal having aperiod of T/2; and a base-4 counter for counting from 0 to 3 accordingto the timing signal to produce the first timing signal every time thebase-4 counter is reset to 0, wherein, when the reference timeinformation has been received, the base-4 counter is reset to 0 togenerate the second timing signal.
 4. The network device according toclaim 1, wherein the timing generator comprises: a binary counter forcounting according to the system clock signal to produce the firsttiming signal every time the binary counter is reset to 0, wherein, whenthe reference time information has been received, the binary counter isreset to 0 to generate the second timing signal.
 5. The network deviceaccording to claim 1, wherein the second timing signal is coincident toa time point when the time information varies in the predetermined timeperiod of T.
 6. The network device according to claim 1, wherein thesecond timing signal is generated independently of a time point when thetime information varies in the predetermined time period of T.
 7. Thenetwork device according to claim 1, wherein N is equal to 2.